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preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice preliminary specification - 1 - ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a04018 t wo p hase v ariable s peed f an m otor c ontroller AMC8500 p roduct s pecification product description the AMC8500 is a full featured monolithic brushless dc motor controller containing all the required functions to implement fan speed control. this device features a selectable slope pulse width modulator (pwm) for efficient speed control with analog and digital control signal compatibility, programmable minimum speed setting, hall amplifier with propriety noise immunity circuitry for proper drive sequencing, fixed non-overlapping commutation delay for reduced supply current spiking, dual on-chip 0.5 ? power mosfets with thermal protection for direct motor drive, programmable cycle-by-cycle current limiting, internal fault timer with auto start retry, motor kick start timer to insure start up, combined frequency generator / rotor lock output, uncommitted op amp with reference for thermal sensor voltage scaling, and a selectable automatic low current power down mode for power sensitive applications. features ? analog and digital speed control signal compatibility ? programmable minimum speed setting ? selectable pwm speed control slope ? latching pwm for enhanced noise immunity ? integrated fault timer with auto start retry ? motor kick start timer ? combined frequency generator / rotor lock output ? differential unbuffered and digital hall compatibility ? hall amplifier with propriety noise immunity circuitry ? pinned out reference ? uncommitted op amp for thermal sensor voltage scaling ? fixed non-overlapping commutation delay ? dual on-chip 0.5 ? mosfet motor drives ? programmable cycle-by-cycle current limit protection ? thermal shutdown protection ? under voltage lockout protection ? selectable automatic low current power down mode applications ? personal computer fans ? workstation and mainframe fans ? lan server blowers ? industrial control system fans ? telcom system fans ? instrumentation test and measurement fans ? card rack fans pin configuration phase 1 output application diagram ordering information part number package operating junction temperature range marking AMC8500de16 soic 16 lead exposed pad AMC8500qs16 qsop 16 lead -40c to 125c AMC8500 ayww ayww ? assembly site year workweek non-inv. inv. commutation logic ?1 v dd 12v h- motor drive current limit h+ fault timer ?2 pwm logic reference op amp slope select signal gnd power gnd ref. output minimum speed speed control fg / rl output current limit set minimum speed set power ground v dd current limit set 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 freq gen. rotor lock AMC8500 reference output non-inverting input inverting input op amp output speed control input slope select hall + hall - phase 2 output signal ground
preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice preliminary specification - 2 - ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a04018 AMC8500 absolute maximum ratings (note 1) parameter symbol rating unit power supply voltage (pin 12) v dd -0.3 to 18 v hall input voltage range (pin 3, 4) v ir(hall) -0.3 to v dd v speed control input voltage range (pin 10) v ir(s) -0.3 to v dd v minimum speed set input voltage range (pin 6) v ir(mss) -0.3 to v dd v reference output load current (pin 5) i o(ref) internally limited ma op amp input voltage range (pin 7, 8) v ir(oa) -0.3 to v dd v op amp output (pin 9, note 4) voltage range source or sink current v or(oa) i o(oa) -0.3 to v dd 30 v ma slope select input voltage range (pin 14) v ir(ls) -0.3 to v ref v current limit set input voltage range (pin 2) v ir(ilim) -0.3 to v ref v frequency generator / rotor lock output (pin 15) voltage range sink current v or(fg/rl) i sink(fg/rl) -0.3 to 18 20 v ma drive outputs (pin 1, 16, note 4) voltage range sink current source current v d(?1/?2) i sink(?1/?2) i source(?1/?2) -0.3v to 36 1.5 -1.5 v a a thermal characteristics sop-16 exposed pad package thermal resistance, junction to air thermal resistance, junction to pad qsop-16 package thermal resistance, junction to air r ?ja r ?jc r ?ja 92 15 136 c/w operating junction temperature range t j(max) -40 c to 125 c storage temperature range t stg -60 c to 150 c ir reflow peak temperature t reflow 260 c lead soldering temperature (10 sec) t lead 300 c electrostatic discharge (note 2) human body model machine model esd 2000 250 v notes: 1. absolute maximum ratings are limits beyond whic h operation may cause permanent damage to the device. these are stress ratings only. functional operation at or above these limits is not implied. 2. human body model: 100 pf capacitor discharged through a 1.5 k resistor into each pin. machine model: 200 pf capacitor di scharged directly into each pin. 3. these specifications are guarante ed only for the test conditions listed. 4. maximum package power dissipation limits must be observed.
preliminary specification AMC8500 electrical characteristics ( v dd = 12 v, t a = 25c, unless otherwise noted. specifications subject to change without notice [note 3].) preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice - 3 - ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a04018 parameter symbol min typ max units speed control (pin 10) and minimum speed set (pin 6) input threshold voltage pin 14 = gnd 0% drive conduction 100% drive conduction pin 14 = open 0% drive conduction 100% drive conduction v th(0%) v th (100%) v th(0%) v th(100%) 0.95 2.85 2.85 0.95 1.0 3.0 3.0 1.0 1.05 3.15 3.15 1.05 v speed control input threshold voltage for power down (i o(ref) 1.0 ma) input voltage below 0% drive conduction, v th(0%) , pin 14 = gnd input voltage above 0% drive conduction, v th(0%) , pin 14 = open v th(pd) - - 20 20 - - mv speed control input pwm signal transition time maximum allowable rise or fall time for digital control t r /t f - - 50 s input bias current, (v in = 3.5 v) i ib - 1.0 - a modulation frequency f pwm - 30 - khz slope select (pin 14) input threshold voltage low state increasing voltage at pin 6, 10 causes increase in drive conduction high state increasing voltage at pin 6, 10 causes decrease in drive conduction v il(s) v ih(s) - 2.8 - - 1.0 - v low state input pull-up current (v il(s) = 0 v) i i(s) - 10 - a hall amplifier (pin 3, 4) input differential voltage sensitivity required signal level to enable drive commutation v id(hall) - 20 40 mvpp input hysteresis voltage (v in = 3.5 v) v ih(hall) - 10 - mv input resistance r in(hall) - 3.0 - m ? input common mode voltage range v icm(hall) 0 to v dd -0.3 to v dd +0.3 - v op amp (pin 7, 8, 9) input offset voltage (v in = 3.5v) v io - 2.0 - mv input bias current (v in = gnd) i ib - 50 - na input common mode voltage range v icm(oa) - 0 to 4.2 - v open loop voltage gain a vol 80 100 - db gain bandwidth product (f = 10 khz) gbw - 70 - khz output voltage swing high state (i source = 5.0 ma to gnd) low state (i sink = 5.0 ma to v dd ) v oh(oa) v ol(oa) - - v dd -1.5 0.5 - - v
preliminary specification AMC8500 preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice reference (pin 5) output voltage (i o = 5.0 ma) v ref 3.325 3.5 3.675 v line regulation (v dd = 6.0 v to 15 v, i o = 5.0 ma) ref line - 2.0 30 mv load regulation (v dd = 6.0 v, i o = 1.0 ma to 10 ma) ref load - 11 30 mv short circuit current (note 4) i sc - 50 - ma reference output load current for automatic power down feature (pin 10 = 500 mv, pin 14 = gnd, t > 2.0s) (pin 10 = 3.5 v, pin 14 = open, t > 2.0s) enabled disabled i o(pd) - 2.0 1.4 1.6 1.0 - ma fault timer drive enabled time during a fault condition t on(flt) - 0.25 - s drive disabled time before restart t off(flt) - 2.0 - s kick start timer motor kick start time (100% duty cycle applied) t on(ks) - 1.0 - s frequency generator / rotor lock (pin 15) low state output sink voltage (i sink = 1.0 ma) v ol(fg/rl) - 0.13 0.25 v off-state leakage current (v off = 12 v) i off(tach) - 0.1 1.0 a minimum hall frequency for rotor lock output high state f rl(min) - 4.0 - hz motor drives (pin 1, 16) low state output voltage (i sink = 500 ma) v ol(drv) - 250 300 mv off-state leakage current (v off = 30 v) i off(drv) - - 5.0 a current limit threshold (pin 2 open, note 4) i lim 900 1100 1300 ma non-overlapping commutation delay t dly(com) - 40 - s total device (pin 12) power supply threshold voltage start-up (v dd increasing) hysteresis (v dd decreasing after turn-on) v th(on) v h - - 4.7 500 - - v mv power supply current operating power down (pin 10 = 0.5 v, i o(ref) 1.0 ma, t > 2.0s, pin 14 = gnd) i s i s(pwrdn) - - 1.6 130 2.0 200 ma a - 4 - ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a04018
preliminary specification AMC8500 preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice - 5 - v in(sc) , speed control input voltage (v) 0 20 40 60 80 100 1.0 2.0 3.0 4.0 0 figure 1- motor drives percent on-time versus speed control input voltage v dd = 12 v pin 14 = gnd t a = 25c minimum speed set shown for 1.5 v, 1.7 v, and 1.9 v. %t on , motor drives percent on-time (%) 5.0 motor turns on/off at min speed setting. auto power down enabled after 1 sec. i o ( ref ) 1.0 ma kick start 1.0 sec. motor remains at min speed setting. auto power down disabled. i o(ref) 2.0 ma 5.0 0 0 20 40 60 80 100 1.0 2.0 3.0 4.0 v dd = 12 v pin 14 = open t a = 25c v in(sc) , speed control input voltage (v) motor remains at min speed setting. auto power down disabled. i o ( ref ) 2.0 ma motor turns on/off at min speed setting. auto power down enabled after 1.0 sec. i o(ref) 1.0 ma minimum speed set shown for 2.1 v, 2.3 v, and 2.5 v. figure 2- motor drives percent on-time versus speed control input voltage %t on , motor drives percent on-time (%) kick start 1.0 sec. 1.95 2.0 2.05 1.0 s/division figure 3- op amp small signal transient response v o , output voltage (v) v dd = 12 v a v = +1.0 r l = 10 m c l = 10 pf t a = 25c 1.5 2.0 2.5 4.0 s/division figure 4- op amp large signal transient response v o , output voltage (v) v dd = 12 v a v = +1.0 r l = 10 m c l = 10 pf t a = 25c figure 5- op amp source and sink output voltage versus current 0 0 1.0 2.0 -1.0 0 i o , out i sink , sink current (ma) 0 0.2 0.4 0.6 0.8 1.0 p ut load current ( ma ) 4.0 8.0 12 v o ( oa ) , out p ut volta g e ( v ) v dd = 12 v t a = 25c 16 -2.0 high state output load to ground low state output load to v dd gnd v dd 1.5 3.0 4.5 0 figure 6- frequency generator / rotor lock low state out p ut volta g e versus sink current v ol(fg/rl) , low state output voltage (v) 6.0 v dd = 12 v t a = 25c ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a04018
preliminary specification AMC8500 preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice figure 8- reference output voltage versus power supply voltage 0 0 1.0 2.0 3.0 4.0 v dd , power supply voltage (v) - 6 - figure 7- reference output voltage change versus output source current -32 -24 -16 -8.0 0 0 i o , reference out ) ( mv p ut source current ( ma ) 4.0 8.0 12 16 v ref , reference out p ut volta g e chan g e v dd = 12 v t a = 25c 20 4.0 8.0 12 v ref , reference output voltage (v) t a = 25c 16 figure 11- phase 1 / phase 2 current limit threshold versus programming voltage 0 0 0.4 0.6 1.0 1.2 v pgm , programming voltage, pin 2 (v) 0.2 0.4 0.6 0.8 i lim , current limit threshold (a) 1.0 0.8 0.2 v dd = 12 v c pin 2 = 10 nf t a = 25c i sink , sink current (a) 0 0.1 0.2 0.3 0.5 0.6 0.2 0.4 0.6 1.0 0 figure 9- phase 1 / phase 2 drive output low state voltage versus sink current v dd = 12 v t a = 25c 1.2 v ol(drv) , low state voltage (v) figure 10- phase 1 / phase 2 drive output on resistance versus power supply voltage 0.4 0.6 0.8 1.0 v dd , power su 0.8 0.4 pp l y volta g e ( v ) r on , drive output on resistance ( ? ) 1816 i sink = 500 ma 0.7 0.9 t = 25 c a 0.5 14 12 10 8.06.04.0 figure 12- programming resistance versus current limit threshold 0 0.4 0.6 1.0 1.2 r pgm , programming resistance ( ? ) 1.0 m i lim , current limit threshold (a) 10 m 0.8 0.2 100 k 10 k v dd = 12 v c pin 2 = 10 nf t = 25c a ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a04018
preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice preliminary specification - 7 - ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a04018 AMC8500 introduction a full featured two phase half wave variab le speed brushless motor controller containing all the required unctional description wn in figure 13 and a detailed discussion on each of the functional blocks and non-inverting input figure 13- representative block diagram the AMC8500 is functions for implementing a fan control system. motor control features consists of a select able slope pulse width modulator (pwm) with double pulse suppression for efficient speed control t hat is compatible with an analog voltage or a varying duty cycle digital pulse train, a programmable minimum speed set input, and an uncommitted op amp with a pinned out reference for speed control signal scaling, hall sensor amplifier with propriety noise immunity circuitry for proper drive sequencing, non-overlapping commutation drive for reduced supply current spiking, on-chip 0.5 ? power mosfets for direct coil drive. protective and diagnostic features include an internal fault time r with auto start retry, motor kick start timer to insure prop er start up, programmable cycle-by-cycle curre nt limiting, power supply under voltag e lockout, and over temperature thermal shutdown, and a combined frequency generator / rotor lock out put for status reporting. also included is a selectable automatic low current power down mode ai med at power sensitive applications. the AMC8500 is designed for use in thermal open or clos ed loop systems. it can be controlled by simple ntc or ptc thermistors, simistor? silicon te mperature sensors, or by complex digital or microcontroller based temperature monitors. f a representative block diagram is sho features are given in the followi ng sections. a complete list of the pin functi ons with a brief description is shown in figure 33. fault timer power down kick start hall amplifier non-overlap commutation current limit comparator motor drives 12 v op amp oscillato r min speed comparato r pwm comparator digital detector r thermal shutdown current limit latch r q s 16 1 12 15 14 10 6 9 8 7 5 11 13 2 pwm logic 10 a hall + input 3 v dd hall - input 4 phase 1 output phase 2 output frequency generator / rotor lock output power g r ou n d current limit set slo p e select si g nal ground speed control input minimum speed set input output inverting input reference output reference under voltage l oc k out h n s s n m
preliminary specification AMC8500 speed control motor speed is efficiently controlled with the use of puls e width modulation, pwm. the voltage applied to the speed control input, pin 10, provides control of motor speed by vary ing the drive percent on-time or conduction time of the phase 1 and phase 2 outputs during the commutation cycle. the control signal can be in the form of an analog voltage ranging from 1.0 v to 3.0 v, or a variable duty cycle digital pulse train ha ving a low state maximum of 0. 98 v, a high state minimum of 3.02 v, with maximum transition times 50 s. the control sign al to pwm transfer slope or speed control input voltage to drive percent on-time, is controlled by the slope select i nput, pin 14. when connected to ground, an increase in control voltage or a digital high state results in an increase in drive output on-time. when unconnected, an increase in control voltage or a digital high state results in a decrease in drive output on-time. preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice a minimum speed set input is made available at pin 6 and it has a control transfer and slope that is identical to that of pin 10. it is designed to be programmed form an analog voltage t hat ranges from 1.0 v to 3. 0 v, which can be derived from the reference. the minimum speed programmed at this input will take control of the motor speed if it is greater than the speed being requested at the speed control input. when directly controlling motor speed from a variable duty cycle digital pulse train, the minimum speed set feature is not available and the comparator input must be disabled. a method for preserving this feature is shown in figure 40. figure 1 shows the motor drives percent on-time versus the speed control input voltage with pin 14 connected to ground for positive slope control. notice that there are two defined outcomes when the speed control input voltage falls below that of the minimum speed set. the first is that the motor contin uously runs at the programmed minimum speed setting and this is selected by loading the reference with 2.0 ma or more to disable auto power down. the second outcome is that the motor turns off after 1.0 second and this is selected by loading the reference wi th 1.0 ma or less to enable auto power down. this gives the fan designer a choice between letting the motor run at a minimum speed or to stop running when speed control falls below the programmed minimum speed setting. figure 2 shows the motor drives percent on-time versus t he speed control input voltage with pin 14 unconnected for negative slope control. the minimum speed operating characteristics are selected in the same manner as above but with the defined outcomes now occurring when the speed control input vo ltage rises above that of the minimum speed set. the speed control and minimum speed operations are shown in table form in figure 14. compatibility with both analog and digital control signals combined with the ability to select both the tr ansfer slope and automatic power down, allows this device to interface into a vast array applications. figure 14- speed control and minimum speed set operation speed control input note that if the end applicat ion does not require a programmed minimum speed or is to be controlled by a variable duty cycle digital pulse train, the minimum speed set comparator must be disabled as shown in figure 28. for applications that do not require speed control, the device can be configured to provide commutation only, yielding maximum motor speed without requiring any additional components. this is accomplish ed by directly grounding pins 6 and 10, while leaving pin 14 open. - 8 - ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a04018 pin 10 signal (v) minimum speed set input pin 6 (v) controlling input slope select pin 14 motor drive (% low) comments 0 to 1.0 0 zero speed, power down mode if i o(ref) 1.0 ma, t > 1.0s. >1.0 to <3.0 0 to 100 %t on = (v sc - 1.0) / 0.02 3.0 to 5.0 gnd (disabled) speed control 100 maximum speed. 0 to <1.7 minimum speed set 35 speed control voltage is less than minimum speed set. >1.7 to 3.0 35 to 100 speed control voltage is greater than minimum speed set. voltage >3.0 to 5.0 1.7 speed control 100 maximum speed. positive pulse pulse <0.98 to >3.02 gnd (disabled) speed control gnd duty cycle positive pulse width duty cycle controlled from pin 10. 5.0 to 3.0 0 zero speed, power down mode if i o(ref) 1.0 ma, t > 1.0s. <3.0 to >1.0 0 to 100 %t on = 100 - (v sc - 1.0 / 0.02) 1.0 to 0 tied to pin 14 (disabled) speed control 100 maximum speed. 3.0 to >2.3 minimum speed set 35 speed control voltage is greater than minimum speed set. <2.3 to 1.0 35 to 100 speed control voltage is less than minimum speed set. voltage <1.0 to 0 2.3 speed control 100 maximum speed. negative pulse pulse >3.02 to <0.98 tied to pin 14 (disabled) speed control open duty cycle negative pulse width duty cycle controlled from pin 10.
preliminary specification AMC8500 hall inputs rotor position is detected by a single hall sensor to enable proper motor drive commutation. the h+ and h- amplifier inputs are designed to interface with a wide variety of econom ical 4 pin unbuffered 'naked' or 3 pin buffered 'digital' hall sensor types. the unbuffered sensors provide a low level differentia l output signal that is directly proportional to the rotors applied magnetic field. the sensor outputs connect directly to the h+ and h- inputs. the amplifier has a differential input sensitivity of 20 mv with a common mode voltage range that extends from v dd to ground. by extending the input range to include ground, the need for offsetting the hall output voltage with a series ground resistor is eliminated. figures 20 through 22 show three methods of biasing unbuffered hall sensors. the AMC8500 hall amplifier featur es enhanced noise rejection by combining a small level of input hysteresis with a propriety zero crossing detector and a timed lockout. preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice the buffered hall sensors provide a high level digital output sign al that changes state in direct response the rotor magnetic pole transitions. this output signal is single ended and can be applied to either the h+ or h- input while biasing the unused input to a level that is within the output voltage swing of the sensors. economical buffered hall sensors typically contain an npn open collector sink only output which requires a pull- up resistor. figures 23 and 24 show two methods for biasing buffered hall sensors. commutation the AMC8500 features a non-overlapping commutation delay circuit that prevents simultaneous drive conduction for reduced power supply current spikes and radio frequenc y interference (rfi). the non-overlap delay time (t dly ) is internally set to 40 s. the commutation waveforms and truth table are shown below in figures 15 and 16. figure 15- two phase, two step, half wave commutation waveforms - 9 - figure 16- commutation truth table x = don?t care hall inputs drive outputs + (pin 3) - (pin 4) system fault phase 1 (pin 16) phase 2 (pin 1) fgrl output (pin 15) low high none off low low high low none low off high x x yes off off high 0 180 360 540 720 rotor electrical position (degrees) full speed (100% pwm) t dly(com) h + h - hall inputs fgrl output voltage phase 2 drain current phase 1 drain voltage phase 2 drain voltage v motor 0 v clamp 0 0 0 phase 1 drain current 0 180 360 540 720 v clamp v motor 0 t dly(com) reduced speed ( 50% pwm) ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a04018
preliminary specification AMC8500 reference a pinned out 3.5 v reference with a tolerance 5.0% is made available to ease the implementation of motor control and allow additional system features. the reference can be used to program the minimum speed set input, provide hall sensor power, or thermal sensor voltage scaling when used in conjunc tion with the uncommitted op amp. the reference output also provides a means to selectively enable or disable the device's automatic low current power down feature. automatic power down is enabled if the output load current is 1.0 ma or less, and disabled if it is 2.0 ma or greater. the reference is a source only output and therefore is not designed to sink current from a higher voltage source. it is capable of sourcing in excess of 10 ma over temperature and has s hort circuit protection. in applications t hat require additional current capability, the output can be buffered with the addition of an external pnp transistor as shown in figure 25. this simple circuit has the advantage of moving any additional regulator power dissipati on off chip but it does not maintain output short circuit protection. preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice op amp a fully compensated op amp with access to both inputs and outpu t is provided to facilitate thermal sensor voltage scaling. the amplifier features a wide input common mode voltage range that extends from ground to 4.2 v, a dc voltage gain of 100 db, and a 70 khz gain bandwidth product. the amplifier outpu t exhibits an voltage swing t hat extends from ground to v dd - 1.7 v, is capable of sinking and sourcing up to 10 ma, and is unity gain stability when driving capacitive loads. in applications where a single amplifier input can exceed the upp er level of the common mode vo ltage range, the output will always maintain the proper state. if both inputs exceed the upper level of the co mmon mode voltage range, a low state output phase reversal can occur and although non destructi ve, it may result in unexpected system behavior. if the intended application does not require use of the op amp, the inputs must be connected to a fixed low impedance source in a manner that will force the output into a defin ed state. this will prevent the possibility of amplifying unwanted noise which can result in erratic circuit behavior. figure 27 shows three suggested connection methods. frequency generator / rotor lock motor speed and fault signals are provided by the frequency generator and rotor lock output at pin 15. these signals can provide diagnostic information to a thermal system contro ller. during normal operation, t he output provides a digital square wave that switches at the hall se nsor commutation frequency. internally, this signal is used to continuously reset the fault timer. if the motor encounters an obst ruction, the decrease in rotational speed will result in a corresponding increase in time between reset pulses. if this time exceeds 0.25 s (t on(flt) ) a fault will be detected, which in turn will terminate motor drive and place pin 15 into a high state, thus indicating a roto r lock condition. after an off time cool down period of 2.0 s (t off(flt) ) has elapsed, the fault timer circuit will apply maximum driv e in attempt to restart the motor for another 0.25 s. this on/off cycling will repeat indefinitely until the motor restarts , or is commanded to stop by the speed control and minimum speed set inputs. upon a successful restart, pin 15 will resume switching at the hall commutation rate after completion of the kick start interval. the frequency generator and rotor lock out put consists of an n-channel open drain device and therefore requires an external pull-up resistor. an internal high gain buffer with hy steresis is used to insure that the output waveform is always rectangular even when the peak to peak hall output signals are at a low level. the operating waveforms are shown in figure 17. figure 17- frequency generator / rotor lock waveforms - 10 - rotor locked or rotating below minimum hall frequency constant speed accelerating constant speed differential hall inputs frequency generator / rotor lock output defaults to high state after fault detected fault timer t off(flt) 2.0 s t on(flt) 0.25 s possible low or high state off fault detected 0.25 s on on off motor d r ives rotor locked rotor free running on retr y cool do w n running cool do w n kick start 1. 0 s ? andigilog, inc. 2006 www.andigilog.com august 2006 - 7 0 a 04018
preliminary specification AMC8500 kick start most dc motors exhibit a large difference between the volt age required to insure startup and minimum speed operation. figure 18 shows this difference as a hysteretic characte ristic and is dependent upon bear ing friction, lubrication, temperature, and rotor inertia. with the majority of motor c ontrollers presently available, the applied voltage for minimum speed operation must be set equal to or gr eater than that required for startup. this limits the motors useful speed range from about 35 to 100 percent even though most mo tors will operate down to 10 percent. in order to guarantee near minimum run speed operation, the mechanical startup hy steresis must be overcome. this is accomplished in the AMC8500 by kick starting the motor in a controlled manner where full power is initially ap plied for a for a prescribed time, and control then reverts ba ck to the level that is dictated by either the speed control or minimum speed set input. this is graphically shown in figures 1 and 2. with reliable starting guaranteed, the useful speed r ange is increased by approximately 25%, yielding lower speed operation for reduced acoustic noise and extended motor life. preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice the kick start time, t on(ks) , is internally set to 1.0 second and is automatic ally activated whenever the motor is at rest and commanded to run, or when it is under a command to run and one of the following events takes place: 1) device comes out of power down mode 2) rotor was locked and the obstruction has cleared 3) device recovered from a thermal shutdown 4) device comes out of an un der voltage lockout condition current limit abnormally high drive current conditions can occur if the moto r is mechanically overloaded and may result in device and the drive coil overheating. during motor overload, any re duction in rotational speed reduces the generated back electromotive force, emf, resulting in an corresponding increase in drive current. the most severe condition occurs when the rotor is locked and there is no back emf generated. under th is condition, the drive curr ent is limited only by the resistance total of the mosfet switch and the driven coil. in order to protect the device and motor from abnormally high currents, a programmable current limit com parator is incorporated. t he comparator indirectly se nses the drive current and when a maximum level is exceeded, the motor drive on-time is immediately terminated on a cycle-by-cycle basis of either the internal oscillator or the digital control signal applied to the speed control input. the current limit threshold defaults to a peak current of 1.1 a with pin 2 open. this level can be reduced by either applying a bias voltage to pin 2 or by connecting a single resistor from this pin to ground. figures 11 and 12 show the current limit behavior while figure 32 illustrates two biasing methods. the current limit set input is high impedance and in most applications will require a 10 nf bypass capacito r to prevent false triggering due to noise pick up. - 11 - ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a04018 %s max , percent maximum motor speed (%) %t on , motor drives percent on-time (%) 100 0 0 20 40 60 80 100 20 40 60 80 kick start extended speed range minimum startup speed 35% on-time minimum run speed 10% on-time kick start 100% voltage 1.0 second figure 18- typical dc motor startup and run characteristics typical useful speed range
preliminary specification AMC8500 motor drives the AMC8500 contains two 0.5 ? n-channel power mosfets that are designed to directly drive the motor coils from the phase 1 and phase 2 outputs. the drive characteristics are sh own in figures 9 and 10. each output contains a 36 v zener with a series diode that connects from the drain to the gate . this configuration provides ac tive clamp protection for the mosfets when switching off the inductive motor load. in applicat ions that demand driving higher current or higher voltage motors, external mosfet power transistors can be used. two examples are shown in figures 29 and 30. although this device is designed to drive two phase half wave motors, a method for driving single phase full wave motors is shown in figure 31. preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice due to the inherent winding coupling that is present in two phase motors, the drain voltage of the off phase will be driven negative and current will be sourced from that output. this current will cause additional device heating and may affect operation of high current motors at elevated ambient temperatures. a simple soluti on is to place the cathode of a low forward drop schottky diode from each drive output to ground. likewise if the motor windings are highly inductive, the internal active clamp will be required to dissipate this energy which will also re sult in additional heating. this too can be eliminated with t he addition of an external zener diode connected from each drai n to ground. the zener breakdown voltage should be in the range of 30 v to 34 v. under voltage lockout and auto power down an under voltage lockout circuit has been incorporated to prevent erratic device operation under low power supply conditions. this circuit enables the motor drives when v dd rises above 4.7 v to guarantee full ic functionality, and disables the drives when v dd falls below 4.2 v. the uvlo circuit has 500 mv of hy steresis to prevent oscillations as the thresholds are crossed during power-up and power-down. the ic is designed to directly drive 9.0 v and 12 v motors. as previously discussed, the device f eatures a selectable auto power down mode. this mode is automatically entered when the voltage applied to the speed control input commands zero or less than zero percent on-time. when entered, the power supply current is reduced from 1.6 ma to 130 a. refer to figures 1, 2, and 14. thermal shutdown internal thermal shutdown circuitry is provided to protect th e device in the event that the maximum junction temperature is exceeded. when activated, typically at 1 40c, the motor drive outputs are disabled to reduce device power dissipation. this feature is intended to prevent ca tastrophic device failures in the event of acci dental overheating. although it is possible to operate the device above the specified maximu m junction temperature of 125c, this pr otection feature is not intended to be used as a substitute for proper thermal system design. when the junction temperature falls below 120c, normal device operation resumes. refer to figure 19. system applications the following section shows numerous device circuit configurat ions and several complete fan control solutions with a brief description. for clarity, many of the circui ts show only the internal functional blo cks that are of interest with the associate d pin numbers. - 12 - ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a04018 figure 19- thermal shutdown operation 80 thermal shut down deactivated motor drives enabled thermal shut down activated motor drives disabled t j(max) t j , junction tem p erature ( c ) 100 120 160 140
preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice preliminary specification ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a04018 AMC8500 - 13 - when powering an unbuffered hall sensor from motor voltage v m , resistor r1 is required. this resi stor sets the hall operating current and places the output within the input common mode voltage range of the hall am p lifier. unbuffered hall sensors that r equire less than 10 ma can be powered directly from the reference output thus eliminating the need for bias resistor r1. this bias method will disable the automatic power down feature if the sensors require more than 2.0 ma. the op amp output can be used as alternative method for powering unbuffered hall sensors that require less than 10 ma. this method eliminates the need for bias resistor r1 while also preserving the automatic power down feature. with this bias method the reference output is essentially unloaded. pull-up resistor r1 is required when using buffered hall sensors that have an open collector output. resistors r2 and r3 bias the unused amplifier input to a level that is within its input common mode range. resistor r1 is required for buffered hall sensors with an open collector output. resistors r2 and r3 can be eliminated by biasing the unused amplifier input from the reference. figure 20- motor supply powered unbuffered hall figure 22- op amp powered unbuffered hall figure 24- reference biased buffered hall with the addition of an economical pnp transistor, the reference output current can be boosted above 100 ma. this simple buffer circuit will not have the benefit of ma intaining short circuit protection. asahi kasei hw-101a r1 h v dd under voltage lockout hall amplifier non-overlap c o m m u tation 12 v m 3 4 h v dd under voltage lockout hall amplifier non-overlap c o m m u tation 12 v m 3 4 toshiba tsh124 reference 9 8 7 5 o p am p v m v dd under voltage lockout hall amplifier non-overlap c o m m u tation 12 3 4 reference 5 ana chip ats177 r1 h figure 21- reference powered unbuffered hall v m h v dd under voltage lockout hall amplifier non-overlap c o m m u tation 12 3 4 toshiba tsh124 reference 5 figure 23- motor supply biased buffered hall ana chip ats177 r1 h v dd under voltage lockout hall amplifier non-overlap commutation 12 v m 3 4 r2 r3 figure 25- reference buffer 5 v m v dd under voltage lockout 12 reference 100 kec kta1270 load 0.1
preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice preliminary specification ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a04018 AMC8500 the op amp can be used to gain up the reference voltage in app lications that require an additional regulated voltage source. th is circuit can supply up to 10 ma for powering additional circuitry or to pr ovide a higher reference voltage. to insure that the op amp ou tput maintains regulation, the maximum programmed output voltage must be less than v dd - 1.7 v. 9 8 7 5 reference - 14 - o p am p r2 r1 v o v o = v ref r2 r1 + 1 comparator configuration with the output forced high. comparator configuration with the output forced low. unity gain amplifier configuration with the output forced low. figure 27- connections if op amp is not required slope select grounded figure 28- connections to disable minimum speed set or digital signal speed control operation slope select open v o max = v dd - 1.7 v 3.5 v op amp 9 8 7 5 reference op amp 9 8 7 5 op amp 9 8 7 5 reference reference 10 a 9 6 reference op amp oscillator min speed comp pwm comp digital detector r 14 1 8 7 5 11 pwm logic reference 10 a 9 6 op amp oscillator min speed comp pwm comp digital detector r 7 14 1 8 5 11 pwm logic if the end application does not require a programmed minimum speed or is to be controlled by a variable duty cycle digital pulse t rain, the minimum speed set comparator must be disabled by connecting pin 6 directly to pin 14. figure 26- higher voltage reference
preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice preliminary specification ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a04018 AMC8500 - 15 - figure 29- driving higher current motors the current limit comparator prot ects the motor drives by limiti ng the output sink current to 1100 ma. in applications that req uire driving higher current motors, the drive current can be significantly increased with the addition of two external p-channel mosfet. cur rent limit protection is not maintained since the load is no longer in series with the internal mosfets. the motor drives are limited to a maximum of 36 v. these outputs can be cascoded with two external n-channel mosfets for drivin g higher voltage motors. the cascode configurat ion maintains current limit protection since the load is in series with the intern al mosfets. hall amplifier non-overlap commutation motor drives 12 v 16 1 12 48 v h 3 4 under vol t age lockout n s s n m figure 3 0 - driv i ng highe r volta g e motors hall amplifier non-ov erlap commutation mot o r driv es 12 v 16 1 12 h 4 under vol t age lockout n s s n m 3
preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice preliminary specification - 16 - ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a04018 AMC8500 figure 31- driving single phase full wave motors figure 32- current limit threshold programming, noise pick up and motor soft acceleration single phase full wave motors can be driven with the addition of two external p-channel mosfets. with the gates cross coupled a s shown above, the internal and external mosfet s can perform as a full bridge driver. co mmutation shoot through current is minimi zed by the internal non-overlapping delay circuit. the resistor capacitor time constant must be just long enough to prevent pulse widt h modulation of the two external pfets. current limit pr otection is maintained since the load is in series with the internal mosfets. the mo tor drive outputs are limited to a maximum of 36 v. the current limit set input is susceptible to noise pick up and in most applications will require a 10 nf bypass capacitor. the current limit comparator threshold can be reduced by connecting a single resistor from pin 2 to ground. this is the most economical programming method but it is somewhat less accu rate than using the dual resistor method s hown. this is due to the fact that the reference output is more accurate than the absolute values of the internal current source pull-up and terminating resistor. mot or soft acceleration during power-up can be accomplis hed by connecting a capacitor from pin 2 to ground. during initial device power-up , the internal current source will charge capacitor c accl thus gradually increasing the current limit threshold. the diode shown is optional and may not be required if there is su fficient time for the internal components to discharge the capacitor from when the power sour ce is removed and then reapplied. hall amplifier non-overlap commutation motor drives 16 1 12 12 v h 3 4 under vol t age lockout n s s n m 10 k 10 k 10 k 10 k 0.1 0.1 current limit comparator current limit latch r q s 13 2 current limit set 10 a 110 k to v m to v ref soft m o t o r a cce l e r a t i o n current li mit thres hold red u c tion single re si stor current sour ce biased dual resi stor ref e renc e biased c accl 10 nf by pass capacitor noise pick up elimina t io n optional
preliminary specification AMC8500 figure 33- pin function description pin function description this output directly drives phase 2 of a unipolar motor. it is active low when the voltage applied to the hall - input exceeds that of hall +. 1 phase 2 output this input is left unconnected for a ma ximum motor drive current sink current of 1100 ma. the sink current can be programmed to a lower level by connecting a resist or from this input to ground. most applications will require a 10 nf bypass capacitor on this pin to prevent noise pick up. 2 current limit set 3 hall + this input connects to the output of an unbuffered differential type hall sensor. 4 hall - this input connects to the output of an unbuffered differential type hall sensor. this is the reference output and is capable of sourcing in excess of 10 ma. it is also used to selectively enable or disable the automatic power down feature. au tomatic power down is enabled if the reference load current is 1.0 ma or less, and disabled if it is 2.0 ma or more. 5 reference output preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice this input is used in conjunction with the reference output to program the minimum motor speed or the threshold for automatic power down. if continuous mi nimum speed operation is desired, the automatic power down feature must be disabled. the minimum speed se t feature is not available when controlling motor speed from a variable duty cycle digital pulse train and th is input must be disabled by connected it to pin 14. 6 minimum speed set 7 non-inverting input this is the non-inverting input of the op amp. it has an operating voltage range that extends from ground to 4.2 v. this is the inverting input of the op amp. it has an operating voltage range that extends from ground to 4.2 v. 8 inverting input this is the op amp output and it is capable of sinki ng or sourcing up to of 10 ma. the op amp can be used in conjunction with the reference for scaling a speed control signal derived from a temperature sensor. 9 op amp output 10 speed control input a voltage level that ranges from 1.0 v to 3.0 v or a variable duty cycle pulse is applied to this input for controlling the motor speed. a positive or negativ e speed control slope can be selected via pin 14. this pin is the ground return for the control circuitry. it connects directly to the po wer source ground terminal. internally this pin connects to the dev ice substrate and the exposed thermal pad. 11 signal gnd 12 v dd this pin is the control circui t positive supply. it connects to t he power source positive terminal. 13 power ground this pin is the ground return for the motor driv e mosfets. it connects to the power source ground terminal. this input selects between a positive or a negativ e speed control slope. when connected to ground, an increasing voltage at pin 6 or 10 increases motor s peed. when not connected, an increasing voltage at pin 6 or 10 decreases motor speed. th is input has an internal 10 a current source pull-up. 14 slope select this output provides a digital square wave signal that switches at the hall sensor frequency and is active low when the voltage applied to the hall - input exceeds that of the hall +. if the motor turns too slow or is stalled, the output will assume a high state. this is an active low open drain output and it requires a pull-up resistor. freq. generator / rotor lock 15 16 phase 1 output layout considerations high frequency printed circuit layout techniques are required to prevent pulse jitter and the possibility of erratic operation. this can be caused by excessive noise pick-up imposed upon the hall or error amplifier inputs. the printed circuit layout should contain as much copper ground as possible with separ ate low current signal and high current motor drive grounds that return back to the power supply input filter capacitor . ceramic 0.1 f bypass capacitors connected close to the integrated circuit v dd and v ref pins may also be required depending upon circuit board layout and the source voltage impedance. the use of bypass capacitors will provide a low impedance path to groun d for filtering out high frequency noise. the signal and power ground pins along with the exposed the rmal pad must be connected together at the package. all high current loops should be kept as short as possible with wide traces to minimize the generati on of radiated electro magnetic interference, emi. wide copper trace connections with copious amounts of foil placed under t he device will greatly enhance the devices ability to dissipate power. - 17 - ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a04018 this output directly drives phase 1 of a unipolar motor. it is active low when the voltage applied to the hall + input exceeds that of hall -.
preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice preliminary specification - 18 - ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a04018 AMC8500 application requirements closest standard 1.0% resistor values thermistor linearization gain offset min speed t min speed pwm t max speed pwm minimum speed setting r1 r2 r3 r4 r5 r6 r7 r8 c %on c %on %on ? ? ? ? ? ? ? ? 30 35 40 100 35 10000 6650 11500 32400 1130 1150 2550 1330 30 67 38 100 35 10000 6980 11500 16200 1870 1330 2550 1330 35 30 50 100 0 10000 4990 15400 29100 1370 1300 - - 37 30 40 100 30 10000 5900 10200 133000 1000 1000 2910 1330 40 30 50 100 30 10000 4640 14700 49900 1000 1000 2910 1330 the op amp used in conjunction with the reference is extremely useful in providing voltage gain and offset to condition the the rmistor signal so that it can drive the speed control input. the table s hows five different application requirements with the calculate d closest standard 1.0% resistor values. in each example, the required mo tor speed or pwm %on is defined for two sensor temperatures alon g with a minimum speed setting. in the third application, the minimum speed set input is not required and the comparator must be disabled by connecting pin 6 to pin 14. note that the total reference load current must exceed 2.0 ma in order to disable the automatic power down feature. 13 7 6 fault timer power down kick start reference hall amplifier non-overlap commutation h current limit comp motor driv es 12 v op amp oscillato r min speed comp pwm comp digital detecto r r thermal shutdow n under voltage lockout current limit latch r q s 16 1 12 15 14 10 9 8 5 11 2 pwm logic 10 a 34 r4 r3 r2 10 k @ 25c = 3694 r6 r5 r7 r8 t r1 n s s n m h h 10 nf figure 34- thermistor sensing variable speed temperature regulator
preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice preliminary specification ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a04018 AMC8500 application requirements closest standard 1.0% resistor values - 19 - gain offset min speed t min speed pwm t max speed pwm minimum speed setting r1 r2 r3 r4 r5 r6 c %on c %on %on ? ? ? ? ? ? 30 35 40 100 35 13700 16500 1400 5360 1070 1130 30 67 38 100 35 10500 76800 1370 6810 1070 1130 35 30 50 100 0 1070 8870 232 845 - - 37 30 40 100 30 1070 48700 1330 4120 1070 1270 40 30 50 100 30 13000 169000 2320 7320 953 1130 this application circuit uses a simistotr? solid state silicon te mperature sensor that provides a precision signal of 10 mv/c with an offset of 500 mv at 0 c. the op amp in conjunction with the reference is used to gain-up and offset the signal before applying it to the speed control input. the above table shows five application requirements that are similar to those in figure 33 with the calcul ated resistor values. the simistor? sensor allows a reduced component count when compared to the equivalent thermistor circuit. in e ach example, the required pwm %on or motor speed is defined for a mi nimum and maximum sensor temperature, and for a minimum speed setting. in the third application, the minimum speed set input is not required and the comparator must be disabled by connectin g pin 6 to pin 14. note that the total reference load current must exceed 2.0 ma in order to disable the automatic power down feature. figure 35- simistor? sensing variable speed temperature regulator 2 10 nf 13 7 6 fault timer power down kick start reference hall amplifier non-overlap commutation h motor drives 12 v current limit comp op amp oscillato r min speed comp pwm com p digital detecto r r thermal shutdown under voltage lockout current limit latch r q s 16 1 12 15 14 10 9 8 5 11 34 pwm logic 10 a r2 r1 r4 r3 r5 r6 n s s n m h asm121 h
preliminary specification AMC8500 preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice - 20 - ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a04018 application requirements closest standard 1.0% resistor values thermistor linearization thre shold hysteresis min speed speed transition temperature c minimum speed setting r1 r2 r3 r4 r5 r6 r7 min to max max to min %on ? ? ? ? ? ? ? 30 28 35 10000 8060 1020 1000 158000 1070 1130 35 30 35 10000 7500 1020 1100 66500 1070 1130 38 35 0 10000 6340 1020 1070 113000 - - 40 38 30 10000 5760 1050 1100 180000 1070 1270 45 40 30 10000 4990 1050 1130 73200 1070 1270 thermostatic control can be accomplished by configuring the op amp as a non-inverting voltage comparator. the above table shows five different application examples with the calculated resistor values. in applications 1, 2, 4, and 5, the motor will switch from the programmed minimum setting to maximum speed as the sensor temperature rises above the required transition temperature. a controlled amount of positive feedba ck shifts the transition temperatures to prov ide thermal hysteresis as the sensor cools. in the third application requirement, the motor speed switches between zero and fu ll speed. in this case the minimum speed set input is not required and the comparator must be disabled by connecting pin 6 to pin 14. note that the total reference load current must exc eed 2.0 ma in order to disable the automatic power down feature. 13 7 6 fault timer power down kick start reference hall amplifier non-overlap commutation h current limit comp motor drives 12 v op amp oscillato r min speed comp pwm comp digital detecto r r thermal shutdown under voltage lockout current limit latch r q s 16 1 12 15 14 10 9 8 5 11 pwm logic 10 a 34 r5 r4 10 k @ 25c = 3694 r2 r1 r6 r7 t r3 n s s n m h h 2 10 nf figure 36- thermistor sensing thermostatic temperature regulator
preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice preliminary specification - 21 - ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a04018 AMC8500 figure 37 simistor? sensing thermostatic temperature regulator application requirements closest standard 1.0% resistor values threshold hysteresis min speed speed transition temperature c minimum speed setting r1 r2 r3 r4 r5 min to max max to min %on ? ? ? ? ? 30 28 35 499 1740 221000 2320 1210 35 30 35 215 715 40200 3240 1690 38 35 0 200 619 60400 - - 40 38 30 187 562 68000 2490 1150 45 40 30 196 562 35700 2490 1150 thermostatic control is achieved by configuring the op amp as a voltage comparat or. the inverting input monitors the simistor? solid state thermal sensor while the non-inverting input is biased to a reference level. the above table shows five different applica tion examples with the calculated resistor values. in applications 1, 2, 4, and 5, the motor speed sw itches from the programmed mini mum setting to maximum as the sensor temperature rises above the r equired transition temperature. a controlled amount of positive f eedback shifts the transition temperatures to provide thermal hysteresis as the sensor cools. in the third application requirement, the motor switches between zero and full speed. in this case the minimum speed set input is not required and the comparator must be disab led by connecting pin 6 to pin 14. note that the total reference load current must exceed 2.0 ma in order to disable the automatic pow er down feature. 6 fault timer power down kick s t ar t reference hall amplifier non-overlap commutation current limit comp motor drives 12 v op amp oscillato r min speed comp pwm comp digital detector r thermal shutdown under voltage lockout current limit latch r q s 16 1 12 15 14 10 9 8 5 11 13 pwm logic 10 a 34 r3 r2 r4 r5 r1 asm121 h h h n s s n m 2 10 nf
preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice preliminary specification ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a04018 AMC8500 - 22 - 4800 40 control signal duty cycle (%) 36 10% 20% 34 32 30 28 26 24 60 80 100 20 0 4000 3200 2400 1600 0 800 min speed set intercept points inlet air temperature c figure 39- fan speed versus control signal duty cycle for various inlet air temperatures fan s p eed ( rpm ) the above circuit controls fan speed in a closed loop manner that is proportional to the control signal duty cycle and inlet ai r temperature. a voltage indicating the required fan speed or refer ence is applied to pin 7 and is derived from the duty cycle to voltage converter and temperature controlled clamp ci rcuits. the duty cycle to voltage converte r consists of an xor gate buffer that dr ives a 10 k, 22 f low pass filter, with the high state level limited by the tem perature controlled clamp. a voltage indicating the actual fan speed or feedback is applied to pin 8 and is derived from the frequen cy to voltage converter that c onsists of two xor gates. th e first xor buffers the fgrl tachometer signal and connects to the second which is configur ed as an edge transition one-shot that drive s a 100 k, 330 nf low pass filter. the op amp co mpares the difference between the refer ence and feedback voltages and generates an error signal that drives pin 6 in a corrective fashion causing t he fan to run either faster or slower so that the feedback volt age level becomes the same as the referenc e. performance data is shown in the above graphs. note that the error signal is applied to pin 6 instead of pin 10 and that pin 10 must be biased between 1.0 v to 3.0 v for proper operation. figure 40- fan speed versus motor voltage for various control signal duty cycles 600 1000 1400 1800 2200 2600 10.8 11.2 11.6 12.0 12.4 12.8 13.2 13.6 70% duty cycle 50% duty cycle 30% duty cycle control signal = 0 to 5.0 v, 10 khz inlet air tem p erature = 30c motor voltage (v) fan s p eed ( rpm ) fgrl out temperature controlled clamp thermisto r (c) 24 25 26 28 30 32 34 36 ( ? ) 10464 10061 9712 9027 8394 7828 7291 6799 = 3300 frequency to voltage converter duty cycle to voltage converter control signal inpu t 2.8 k 150 k 10 nf 6.8 k 10 k 100 k 47 k 20 k 330 nf 1 m 15 9 under voltage lockout reference op amp hall amplifier non-overlap commutation fault timer power down kick start current limit latch thermal shutdown r s q current limit comp 10 a pwm logic motor drives digital detector oscillato r pwm comp min speed comp 5 7 8 6 10 11 14 13 1 16 4 3 12 12 v t 6.8 k h h 10 k 10 k 22 f 330 nf 10 k v dd error fb ref sc 74ac86pc 100 nf h n s s n m 2 10 nf figure 38- balanced technology extended (btx) closed loop speed control
preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice preliminary specification ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a04018 AMC8500 figure 42- speed control alarm min speed com - 23 - p pwm comp reference op amp osc ill ator r 10 6 9 8 7 5 r2 r1 v th speed alarm output v th 0 v 3.0 v v ol v oh speed control input pin 11 = gnd v th = 1 + 0.02(%ton) pin 11 = open v th = 3 - 0.02(%ton) r2/r1 = (v ref / v th ) - 1 min speed com p pwm comp r1 reference op amp osc ill ator r 10 6 9 8 7 5 r2 v th speed alarm output v th 0 v 3.0 v speed control input v ol v oh the programmable minimum speed set featur e can be preserved when controlling motor speed from a varying duty cycle pulse. the above circuit uses transistor q1, capacitor c1 and the referenc e to convert the digital control signal to an analog voltage. wi th the resistor values shown, the voltage at pin 10 varies between 3.0 v with q1 off and 1.0 v with q1 on, which represents a pwm on-t ime of 0% and 100% respectively. the value of capacitor c1 is dependent upon the pulse frequency and should be sized be so that the ri pple at pin 10 is less than 10 mv. the op amp is not required in th is application and is connected as a unity gain follower with the non- inverting grounded. the minimum speed set input is programmed for a pwm on-time of approximately 33%. since the reference is always required, the programming resistors also provide a load that exceeds 2.0 ma for disabling the automatic power down featu re. the op amp and reference can be used to generate a speed control alarm signal. resistors r1 and r2 divide down the reference output voltage to set trip threshold v th . the op amp compares the speed control input voltage to the trip threshold and the output changes state when it is cross ed. in the circuit on the left, the speed alarm out put transitions from a low to high state as th e speed control input voltage increases. with the ci rcuit on the right, the speed alarm output tran sitions from a high to low state as the speed control input voltage increases. threshold hysteresis can be added to the circuit on the right by placing a resistor from pin 9 to pin 7. 909 36 k 12 v pulse input 13 7 6 fault timer power down ki c k sta r t reference hall amplifier non-overlap co mm utat i o n h current limit comp motor drives op amp oscillato r min speed comp pwm com p digital detecto r r thermal shutdown under voltage lockout current limit latch r q s 16 1 12 15 14 10 9 8 5 11 2 n s s n m 34 pwm logic c1 0.1 2.7 k 10 k 6.2 k 453 q1 10 nf 10 a figure 41- digital pulse speed control with programmable minimum speed set
preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice preliminary specification ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a04018 AMC8500 in applications that require increased system reliability, multip le cooling fans can be employed for redundancy. in this exampl e two AMC8500s are cross coupled so that each device drives a fan wh ile monitoring operation of the other. resistors r2 and r3 progra m the speed control inputs to operate each fan at a 50% speed. during normal operation, the frequency generator / rotor lock outputs, pin 15, continuously discharges their respective c1 capacitors. in the event that one fan should fail, pin 15 will allow r1 to charge c1 above 2.0 v. this causes the op amp output to drive the minimum speed set input above 3.0 v for maximum speed on the remaining fan. the values for resistors r2 and r3 are chosen so that each reference output is loaded in excess of 2.0 ma in order to disa ble the automatic power down feature. figure 43- dual fan redundancy r2 590 r1 1.0 m r2 590 - 24 - timers power down ref hall amp commutation h drives 12 v current limit op amp osc min spd pwm digital detector tsd uvlo latch r q s 16 1 15 14 10 6 9 8 7 5 11 13 2 pwm logic 10 a 3 4 12 timers power down ref hall amp commutation h current limit drives 12 v op amp osc min spd pwm digital detector tsd uvlo latch r q s 16 1 15 14 10 6 9 8 7 5 11 13 2 pwm logic 10 a 3 4 12 r3 787 c1 1.0 r3 787 c1 1.0 r1 1.0 m m m 10 nf 10 nf
preliminary specification AMC8500 preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice - 25 - ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a04018 top view bottom view side view end view detail a figure 44- qsop16 package outline drawing
preliminary specification AMC8500 preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice - 26 - ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a04018 figure 45- soic16 exposed pad package outline drawing
preliminary specification AMC8500 data sheet classifications preliminary specification this classification is shown on the heading of each page of a specification for produc ts that are either under development (design and qualification), or in the formative planning stages. andigilog reserves the right to change or discontinue these products without notice. new release specification preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice this classification is shown on the heading of the first page only of a specification for products that are either under the later stages of development (characterization an d qualification), or in the early weeks of release to production. andigilog reserves the right to change the specification and information for these products without notice. fully released specification fully released datasheets do not contain any classifica tion in the first page header. these documents contain specification on products that are in full production. andigilog will not change any guaranteed limits without written notice to the customers. obsolete datasheets that were written prior to january 1, 2001 without any header classification information should be considered as ob solete and non-active specifications, or in the best case as preliminary specifications. life support policy andigilog's products are not authorized for use as critical components in life support devices or systems without the express written approval of the president and general counsel of andigilog, inc. as used herein: 1. life support devices or systems are dev ices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. andigilog, inc. 8380 s. kyrene rd., suite 101 tempe, arizona 85284 tel: (480) 940-6200 fax: (480) 940-4255 - 27 - ? andigilog, inc. 2006 www.andigilog.com august 2006 - 70a04018

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